使用(yòng)Quartus進(jìn)行編譯的(de)过(guò)程中(zhōng)，出(chū)現(xiàn)以(yǐ)下(xià)報錯，Verilog HDL Procedural Assignment error at tb.v(20): object "cap_flow" on left-hand side of assignment must have a variable data type



答(dá)：一(yī)般都是(shì)信(xìn)号(hào)類(lèi)型定(dìng)義出(chū)錯，原来(lái)定(dìng)義为(wèi)wire改为(wèi)reg，或(huò)者(zhě)reg的(de)改为(wèi)wire，請看(kàn)：http://fpgabbs.com/forum.php?mod ... =621&fromuid=100110