【文(wén)章(zhāng)】SDRAM控制器_自(zì)動(dòng)刷新設計(jì)

module sdram_top(

clk    ,

sys_rst_n  ,

//其它(tā)信(xìn)号(hào),舉例dout

local_addr,

local_data,

local_q,

local_rdreq,

local_wrreq,

local_reday,

local_rdata_vaild,

init_done,

sdr_cke,

sdr_cs_n,

sdr_ras_n,

sdr_cas_n,

sdr_we_n,

sdr_ba,

sdr_a,

sdr_dq,

sdr_dqm,

sdr_clk

);

input clk;

input sys_rst_n;

input [24:0] local_addr;

input [63:0] local_data;

output [63:0] local_q;

input local_rdreq;

input local_wrreq;

output local_reday;

output local_rdata_vaild;

output init_done;

output sdr_cke;

output sdr_cs_n;

output sdr_ras_n;

output sdr_cas_n;

output sdr_we_n;

output [1:0] sdr_ba;

output [12:0] sdr_a;

output [15:0] sdr_dq;

output [1:0] sdr_dqm;

output sdr_clk;

wire phy_clk;

wire rst_n;

wire rt_flag;

wire rt_clear;

wire rt_en;

wire ref_en;

wire ref_done;

wire sel_sm;

wire [19:0] sdr_bus;

wire [19:0] init_bus;

wire [19:0] ref_bus;

assign {sdr_cke, sdr_cs_n, sdr_ras_n, sdr_cas_n, sdr_we_n, sdr_ba, sdr_a} = sdr_bus;

assign sdr_dqm = 2'b00;

sdram_init sdram_init_inst(

.clk            (phy_clk)       ,

.rst_n          (rst_n)       ,

//其它(tā)信(xìn)号(hào),舉例dout

.init_done      (init_done)       ,

.init_bus       (init_bus)

);

arbitrate arbitrate_inst(

.clk(phy_clk),

.rst_n(rst_n),

.rt_en(rt_en),

.rt_flag(rt_flag),

.init_done(init_done),

.ref_done(ref_done),

.ref_en(ref_en),

.sel_sm(sel_sm),

.rt_clear(rt_clear)

);

ref_timer ref_timer_inst(

.clk(phy_clk),

.rst_n(rst_n),

.rt_en(rt_en),

.rt_clear(rt_clear),

.rt_flag(rt_flag)

);

sdram_ref sdram_ref_inst(

.clk(phy_clk),

.rst_n(rst_n),

.ref_en(ref_en),

.ref_done(ref_done),

.ref_bus(ref_bus)

);

sdram_mux sdram_mux_inst(

.clk(phy_clk),

.rst_n(rst_n),

.init_bus(init_bus),

.ref_bus(ref_bus),

.sdr_bus(sdr_bus),

.sel_sm(sel_sm)

);

my_pll PLL(

.areset (~sys_rst_n) ,

.inclk0 (clk) ,

.c0 (phy_clk) ,

.c1 (sdr_clk) ,

.locked (rst_n)

);

endmodule

module arbitrate(clk, rst_n, rt_en, rt_flag, init_done, ref_done, ref_en, sel_sm, rt_clear);

input clk;

input rst_n;

input rt_flag;

input init_done;

input ref_done;

output reg rt_en;

output reg ref_en;

output reg sel_sm;

output reg rt_clear;

localparam SM_INIT = 1'b0;

localparam SM_REF  = 1'b1;

always @(posedge clk or negedge rst_n)begin

if(!rst_n)begin

rt_en <= 1'b0;

end

else if(init_done)begin

rt_en <= 1'b1;

end

else begin

rt_en <= rt_en;

end

end

always @(posedge clk or negedge rst_n)begin

if(!rst_n)begin

ref_en <= 1'b0;

end

else if(rt_flag)begin

ref_en <= 1'b1;

end

else if(ref_done)begin

ref_en <= 1'b0;

end

else begin

ref_en <= ref_en;

end

end

always @(posedge clk or negedge rst_n)begin

if(!rst_n)begin

sel_sm <= SM_INIT;

end

else if(init_done)begin

sel_sm <= SM_REF;

end

else begin

sel_sm <= sel_sm;

end

end

always @(posedge clk or negedge rst_n)begin

if(!rst_n)begin

rt_clear <= 1'b0;

end

else if(rt_flag)begin

rt_clear <= 1'b1;

end

else begin

rt_clear <= 1'b0;

end

end

endmodule

module ref_timer(clk, rst_n, rt_en, rt_clear, rt_flag);

input clk;

input rst_n;

input rt_en;

input rt_clear;

output reg rt_flag;

parameter CNT_MAX = 750;

reg [9:0] cnt;

wire add_cnt;

wire end_cnt;

always @(posedge clk or negedge rst_n)begin

if(!rst_n)begin

cnt <= 0;

end

else if(add_cnt)begin

if(end_cnt)

cnt <= 0;

else

cnt <= cnt + 1;

end

end

assign add_cnt = rt_en;

assign end_cnt = add_cnt && cnt==CNT_MAX - 1 ;

always @(posedge clk or negedge rst_n)begin

if (!rst_n)

rt_flag <= 0;

else if (add_cnt && cnt == CNT_MAX - 1)

rt_flag <= 1;

else if (rt_clear)

rt_flag <= 0;

else

rt_flag <= rt_flag;

end

endmodule

module sdram_ref(clk, rst_n, ref_en, ref_done, ref_bus);

input clk;

input rst_n;

input ref_en;

output reg ref_done;

output [19:0] ref_bus;

parameter CNT_MAX = 9;

// parameter TRP = 2;

// parameter TRFC = 7;

parameter NOP = 4'b0111;

parameter PRE = 4'b0010;

parameter REF = 4'b0001;

reg [3:0] cnt;

reg [3:0] sdr_cmd;

reg [1:0] sdr_ba;

reg [12:0] sdr_a;

wire add_cnt;

wire end_cnt;

assign sdr_cke = 1'b1;

assign ref_bus = {sdr_cke, sdr_cmd, sdr_ba, sdr_a};

always @(posedge clk or negedge rst_n)begin

if(!rst_n)begin

cnt <= 0;

end

else if(add_cnt)begin

if(end_cnt)

cnt <= 0;

else

cnt <= cnt + 1;

end

end

assign add_cnt = ref_en;

assign end_cnt = add_cnt && cnt==CNT_MAX - 1 ;

always @(posedge clk or negedge rst_n)begin

if(!rst_n)begin

sdr_cmd <= NOP;

end

else if(ref_en && add_cnt && cnt == 0)begin

sdr_cmd <= PRE;

end

else if(add_cnt && cnt == 2 - 1)begin

sdr_cmd <= REF;

end

else begin

sdr_cmd <= NOP;

end

end

always @(posedge clk or negedge rst_n)begin

if(!rst_n)begin

sdr_a <= 13'd0;

end

else if(ref_en && add_cnt && cnt == 0)begin

sdr_a[10] <= 1'b1;

end

else begin

sdr_a <= 13'd0;

end

end

always @(posedge clk or negedge rst_n)begin

if(!rst_n)begin

ref_done <= 1'b0;

end

else if(add_cnt && cnt == CNT_MAX - 1)begin

ref_done <= 1'b1;

end

else begin

ref_done <= 1'b0;

end

end

endmodule

module sdram_mux(clk, rst_n, init_bus, ref_bus, sdr_bus, sel_sm);

input clk;

input rst_n;

input [19:0] init_bus;

input [19:0] ref_bus;

output reg [19:0] sdr_bus;

input sel_sm;

localparam SM_INIT = 1'b0;

localparam SM_REF  = 1'b1;

always @(posedge clk or negedge rst_n)begin

if(!rst_n)begin

sdr_bus <= init_bus;

end

else if(sel_sm == SM_INIT)begin

sdr_bus <= init_bus;

end

else if(sel_sm == SM_REF)begin

sdr_bus <= ref_bus;

end

else begin

sdr_bus <= sdr_bus;

end

end

endmodule